The invention relates to a method for the parallel input of data in the form of a test pattern into storage cells of a semiconductor memory, and to a circuit configuration in particular for the implementation of the method, including a semiconductor memory having a least one block of 2.sup.N+M storage cells disposed in the form of a matrix, word lines and internal bit lines through which the storage cells can be addressed, word line decoders for activating the word lines, and bit line decoders for activating the internal bit lines, an internal evaluator circuit assigned to each internal bit line for dividing the internal bit lines into two halves, a transfer transistor pair connecting each internal evaluator circuit to an external collective bit line common to all of the transfer transistor pairs, and an external evaluator circuit connected the external collective bit line on one hand for amplifying data read out from the semiconductor memory and for finally transmitting the amplified data, and on the other hand for receiving data input into the semiconductor memory from a data input circuit in the form of logic levels and for transferring this data to the external collective bit line.
Semiconductor memories, in particular integrated semiconductor memories of the RAM-type (DRAM, SRAM) currently have a large storage capacity (e.g. 1MB.times.1). In the past the storage capacity which can be attained has quadrupled every three to four years. Regarding the testing of such semiconductor memories, it is known that the time required to perform the tests in dependence upon the test patterns to be applied to the semiconductor memory increases at least by a factor of 2.sup.N with an increase in the storage size of a factor N.
In order to save test time, European Patent Application No. 01 86 040, corresponding to allowed U.S. application Ser. No. 811,932 has proposed that a semiconductor memory be internally divided into a plurality of identical blocks, that these be operated in parallel during test operation, and that the majority of the possibly occurring faults be detected through an analysis circuit. In practice it is possible to divide a semiconductor memory into four or eight identical blocks along these lines without any noticeable increase in the additional outlay of wiring and circuitry. However, division into substantially more blocks necessitates an increased additional outlay of circuitry and wiring which, in the case of integrated semiconductor memories, has a negative influence, in particular on the base or chip surface area requirement. U.S. Pat. No. 4,055,754 discloses a test circuit which permits a column-parallel readout of all of the storage cells of one single word line, wherein all of the storage cells of the word line which is to be read are to contain the same information. However, information is input into the storage cells in a traditional fashion.
It is accordingly an object of the invention to provide a method and circuit configuration for the parallel input of data into a semiconductor memory, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type and which permits storage cells of a semiconductor memory to be written into in the shortest possible time with the least possible additional outlay of circuitry and space in comparison to prior art semiconductor memories.